1. Field of the Invention
The present invention relates to an input circuit, an output circuit and an input-output circuit for transmitting a signal between semiconductor devices connected through transmission lines and more particularly to an input circuit, an output circuit and an input-output circuit (hereinafter referred to as an interfacing circuit) enabling signal transmission (or signal interfacing) to be performed at high speed and with less power consumption.
2. Description of the Related Art
In recent years, small-amplitude interfacing specifications including GTL (Gunning Transceiver Logic), CTT (Center Tapped Termination), LVDS (Low Voltage Differential Signaling), PECL (Pseudo Emitter Coupled Logic), PCML and the like are increasingly used for transmitting signals through transmission paths such as bus lines between semiconductor devices composed of two or more integrated circuits.
In the conventional signal transmission, a signal used for the transmission has an amplitude being near to that of a supply voltage being applied to integrated circuits. However, in the interfacing specifications described above, a signal having a specified amplitude which is converted to a small level is transmitted. Taking a case of CMOS (Complementary Metal Oxide Semiconductor) interfacing as an example, an amplitude of a signal being transmitted by the conventional method is generally about 5 V or 3 V, which is approximately equal to that of a supply power voltage applied to integrated circuits or the like.
However, for example, in the case of the LVDS (Low Voltage Differential Signaling) interfacing specifications, an amplitude of a signal to be transmitted is as small as about 0.3 V. In the case of the PECL interfacing specifications, it is about 0.6V.
The reason for making an amplitude of a transmission signal small is that it is clearly attributable to an increase of the transmission speed, lowering of the power consumption and reduction of noise.
In the case of the PECL interfacing specifications, for example, a high-level small-amplitude signal can be generated by allowing a specified current to flow, in an output circuit, through a terminating resistor to a terminating voltage source and thereby producing electromotive force with a specified terminating resistor, while a low-level small-amplitude signal can be generated by allowing a specified current to flow, in an output circuit, through a resistor from a terminating voltage source and thereby producing electromotive force with a specified terminating resistor. Accordingly, a high-level small-amplitude signal to be produced has a voltage level being lower by about 0.3 V with respect to the terminating voltage while a low-level small-amplitude signal has a voltage level being lower by about 0.3 V as well. As a result, a signal having an amplitude of about 0.6 V is produced.
In general, two methods are available for transmitting such small-amplitude signals, one being a single-phase transmission system and the other being a differential-phase transmission system. In the case of the single-phase transmission system, only one small-amplitude signal is used for signal transmitting. On the other hand, in the case of the differential-phase transmission system, in addition to one small-amplitude signal being equivalent to that used by the single-phase transmission system, another small-amplitude signal being in inverse phase is transmitted at the same time, i.e., two small-amplitude signals are simultaneously transmitted.
When a signal is received by the single-phase transmission system, to one of two input terminals mounted on a receiving circuit is supplied a reference voltage being near to a center voltage of an amplitude of the signal and to the other input terminal is inputted the transmission signal, and if the transmission signal having a voltage being higher than the reference voltage is supplied, the transmission signal is judged to be a high-level signal and if the transmission signal having a voltage being lower than the reference voltage is supplied, the signal is judged to be a low-level signal.
When a signal is received by the differential-phase system, two small-amplitude signals including one not being in inverse phase and the other being in inverse phase are transmitted simultaneously and these two signals are inputted to two input terminals mounted on the receiving circuit as they are. If the voltage of the signal inputted to an inversion-phase input terminal is higher than that of the signal inputted to an positive-phase input terminal, the signal is judged to be high, and if the voltage of the signal inputted to the inversion-phase input terminal is lower than that of the signal inputted to the positive-phase input terminal, the signal is judged to be low. The description hereafter is made according to an example using the differential-phase input terminal.
FIG. 7 is a schematic diagram showing one example of a conventional input-output circuit. As shown in FIG. 7, in the input-output circuit, a sending (controlling) integrated circuit 1 is connected through transmission lines 4 and input terminals IN and INB to a receiving (controlled) integrated circuit 2. The integrated circuit 1 has an output circuit 3 adapted to convert, for example, logic signals inputted from an inputting circuit (not shown) or logic signals or the like used to control the integrated circuit 2, to small-amplitude signals and to output the converted signals. The integrated circuit 2 has an input circuit 5 adapted to amplify small-amplitude signals inputted from the integrated circuit 1 to a predetermined amplitude level and a CMOS internal circuit 6 mounted on the same chip as the input circuit 5 is mounted and operated in accordance with a signal fed from the input circuit 5. Each line of the transmission lines 4 is connected to each of terminating resistors Rt and is terminated at a terminating voltage (Vtt) with these terminating resistors Rt. Moreover, there are some interfacing specifications where the terminating resistor Rt is used, however, the terminating voltage Vtt is not applied.
FIG. 8 is a schematic diagram showing one specific example of a conventional input circuit. This conventional circuit is adapted to convert small-amplitude signals (i.e., logic signals or the like to control the CMOS internal circuit 6) fed through the transmission lines 4 from the sending (controlling) integrated circuit 1 to a signal having a predetermined amplitude (VDD full-swing amplitude).
Referring to FIG. 8, signals supplied from the transmission lines 4 are fed to each of gates of p-chanel MOS transistors (hereinafter referred simply to as a pMOS transistor) P1 and P2 constituting an amplifying circuit 21 of the input circuit and the signal amplified by the amplifying circuit 21 is fed through a NodeA to an inverter circuit 22, and the logic signal that has not yet been converted to a small-amplitude signal is fetched from the inverter circuit 22 by the sending (controlling) integrated circuit 1. Moreover, the amplifying circuit 21 and the inverter circuit 22 are formed on the same integrated circuit (a chip).
The amplifying circuit 21 is comprised of a constant current circuit II, pMOS transistors P1 and P2, and nMOS transistors N1 and N2. A drain of the pMOS transistor P1 is connected to a drain of the nMOS transistor N2 and a source of the nMOS transistor N2 is connected to a predetermined reference potential point GND of the receiving (controlled) integrated circuit 2. Similarly, a drain of the pMOS P2 is connected to a drain of the nMOS transistor N1 and a source of the nMOS transistor N1 is connected to the reference potential point GND. Moreover, the drain of the nMOS transistor N1 (the drain of the pMOS transistor P2) is connected to gates of the nMOS transistor N1 and the nMOS transistor N2, and drains of the pMOS transistor P1 and the pMOS transistor P2 are connected through the constant current circuit II to a predetermined direct current supply source VDD of the receiving (controlled) integrated circuit 2.
The inverter circuit 22 is comprised of a pMOS transistor P3 and an nMOS transistor N3. A drain of the pMOS transistor P3 is connected to a drain of the nMOS transistor N3, a source of the nMOS transistor N3 is connected to a reference potential point GND and a drain of the pMOS transistor P3 is connected to a direct voltage supply source VDD. Moreover, the drain of the pMOS transistor P1 (the drain of the nMOS transistor N3) constituting the amplifying circuit 21 is connected through the NodeA to gates of the pMOS transistor P3 and of the nMOS transistor N3 constituting the inverter circuit 22.
Next, by referring to FIG. 9, operations of the conventional input circuit 5 are described. FIG. 9 is a timing chart explaining states of signals flowing each part of the input circuit of FIG. 8.
When small-amplitude signals (such as logic signals or the like), as shown in (a) portion in FIG. 9, are inputted to two input terminals IN and INB of the circuit shown in FIG. 8 through the transmission lines 4 from the sending (controlling) integrated circuit 1, during a period 1 in FIG. 9, the pMOS transistor P1 and nMOS transistor N3 are turned OFF and the pMOS transistor P2 and pMOS transistor P3 are turned ON. During a period 2 in FIG. 9, the pMOS transistor P1 is changed from an OFF state to ON state and the pMOS transistor P2 is gradually changed from an ON to OFF state. During a period 3 in FIG. 9, the pMOS transistor P1 and nMOS transistor N3 are turned ON and the pMOS transistor P2 and pMOS transistor P3 are turned OFF. During a period 4 in FIG. 9, the pMOS transistor P1 is changed from an ON state to OFF state and the pMOS transistor P2 is gradually changed from an OFF state to ON state. During a period 5 in FIG. 9, the pMOS transistor P1 and nMOS transistor N3 are turned OFF and the pMOS transistor P2 and pMOS transistor P3 are turned ON.
After small-amplitude signals (such as logic signals or the like) as shown in (a) portion in FIG. 9, inputted through the two input terminals IN and INB shown in FIG. 8, and via the transmission lines 4 by the sending (controlling) integrated circuit 1a are fed to gates of the pMOS transistors P1 and P2 constituting the amplifying circuit 21, the signals received by the amplifying circuit 21 are transmitted, as shown in (b) portion of FIG. 9, through the NodeA to gates of the pMOS transistor P3 and the nMOS transistor N3. Then, as shown in (c) portion of FIG. 9, the inverter circuit 22 feeds the small-amplitude signals (logic signals or the like to control the CMOS internal circuit 6) supplied via the transmission lines 4 by the sending (controlling) integrated circuit 1 and converted to logic signals each having a predetermined amplitude (VDD full-swing amplitude) to the CMOS internal circuit 6.
Electrical characteristics of transistors formed within the integrated circuit usually are varied due to circuit characteristic variation factors (such as power supply voltages, temperatures and manufacturing processes), and their logic thresholds are varied in a CMOS logic circuit (the inverter circuit 22) in particular. This presents a problem in that a shift occurs in timing for ON/OFF of transistors used in the inverter circuit in particular. Though the amplifying circuit 21 is also affected by the variations in logic threshold voltage caused by variations in the processes of manufacturing the transistors, its influence is less compared with the inverter circuit 22 and therefore only the influence on the inverter circuit 22 is taken into consideration in the descriptions thereafter.
After the small-amplitude signals (i.e., logic signals or the like), as shown in (a) portion of FIG. 9, are inputted to the input terminal IN and INB, if the amplitude levels of the small-amplitude signals inputted to the input terminal IN and INB are inverted during a period between (I) to (III) points, a signal, the amplitude level of which is changed from a level at (I) point to a level at (III) point, as shown in (b) portion of FIG. 9, is fed by the amplifying circuit 21 to the inverter circuit 22 via NodeA. In the (a) portion of FIG. 9, the characters "Voff" represent an amplitude center voltage of the small-amplitude signal and the characters "Vdm" represent an amplitude level of the small-amplitude signal. Moreover, values of the "Voff" and "Vdm" have been predetermined or defined by the above-mentioned small-amplitude interfacing specifications (such as GTL, CTT, LVDS, PECL, PCML or the like).
At this point, if variations in the logic threshold level caused by variations in manufacturing processes do not occur in transistors constituting the inverter circuit 22, the signal inversion point voltage of the inverter circuit 22 becomes the threshold value A shown in (b) portion in FIG. 9 and, as shown in (c) portion of FIG. 9, the output of the inverter circuit 22 is_inverted from VDD level to 0 (zero) volts at the amplitude level_(threshold value A) of the signal flowing through the NodeA at_the point (II)_of FIG. 9. Similarly, the output of the inverter_circuit 22 is inverted from 0 (zero) volts to VDD level at the_amplitude level (the same threshold value A) of the signal flowing the NodeA at the point (II)_. As a result, during a point between (I) to (V), a rectangular wave, the amplitude level of which is changed from VDD level to 0 (zero) volts, is supplied through the terminal "OUT" to the CMOS internal circuit 6.
On the other hand, even if variations in the logic threshold level caused by variations in manufacturing processes occur in transistors constituting the inverter circuit 22, when the signal inversion point voltage of the inverter circuit 22 becomes high, as shown in (d) in FIG. 9, the_output of the inverter circuit 22 is_inverted from VDD level to 0 (zero) volts at the amplitude level_(threshold value B=value higher than proper level) of the signal_flowing through the NodeA during a period between (II) and (III)_points of FIG. 9. Similarly, the output of the inverter circuit 22 is inverted from 0 (zero) volts to VDD level at the amplitude level_(the same threshold value B) of the signal flowing the NodeA_during a period between (IV) and (V) points in FIG. 9.
As a result, a rectangular wave in which the amplitude level is changed from VDD level to 0 (zero) volts during a period from a point when an amplitude level of a signal flowing through the NodeA reaches a threshold value B during a period between (II) and (III) points to a point when an amplitude level of a signal flowing the NodeA reaches a threshold value B during a period between (IV) and (V) points as shown in (b) portion in FIG. 9, i.e., in which delay time variation factors represented as "skew B" in (d) portion as shown in FIG. 9 when the inverter threshold value is at the point B being higher than the proper value A as shown in (c) portion in FIG. 9, occur at the time of a rise and a fall of the signal, is supplied through a terminal OUT to the CMOS internal circuit 6.
Similarly, even if variations in the logic threshold level caused by variations in manufacturing processes occur in transistors constituting the inverter circuit 22, when the signal inversion point voltage (threshold value) of the inverter circuit 22 becomes low, for example, as shown in (e) in FIG. 9, the output of the inverter circuit 22 is inverted from VDD level to 0 (zero) volts at the amplitude level (threshold value C=value lower than proper level) of the signal flowing through the NodeA_during a period between (I) and (II) points. Similarly, a case may occur where the output of the inverter circuit 22 is inverted from 0 (zero) volts to VDD level at the amplitude level (at the threshold value C) of the signal flowing the NodeA during a period between (V) and (VI) points in FIG. 9.
As a result, a rectangular wave in which the amplitude level is changed from VDD level to 0 (zero) volts during a period from a point when an amplitude level of a signal flowing through the NodeA reaches a threshold value C during a period between (I) and (II) points to a point when an amplitude level of a signal flowing the NodeA reaches a threshold value C during a period between (V) and (VI) points as shown in (b) portion in FIG. 9, i.e., in which time variation factors represented as "skew C" as shown in (e) portion in FIG. 9 when the inverter threshold value is at the point C being lower than the proper value A, occur at the time of a rise and a fall of the signal, is supplied through a terminal OUT to the CMOS internal circuit 6.
However, the conventional input-output circuit presents a problem in that, if variations in the logic threshold level caused by variations in manufacturing processes occur in transistors constituting the inverter circuit, when a logic signal is outputted from the inverter circuit to an internal circuit composed of later stage logic circuits or the like, the "skew" (delay time variation factor) occurs in output logic signals. If this occurs, when a period during which the logic signal outputted to the internal circuit remains ON or OFF is shorter than a minimum period, i.e., a minimum pulse period, during which a high or low level signal can be recognized, it is impossible for the internal circuit to exactly recognize the logic signal supplied.